FIG. 1A illustrates a conventional system for arbitration of parallel multi-event processing. As shown in FIG. 1A, the conventional system includes a plurality hardware engines, a plurality of hardware components, and an associated arbitration logic associated with each of the plurality of hardware components. The plurality of hardware engines are represented by hardware engine A 102, hardware engine M 104, and hardware engine Y 106. The plurality of hardware components are represented by hardware component A 108 and hardware component Y 110. The arbitration logic A 108a is associated with the hardware component A 108. Similarly, the arbitration logic Y 110a is associated with the hardware component Y 110.
When one or more of the plurality of hardware engines need to access a hardware component in the plurality of hardware components, a request is made to the arbitration logic associated with the hardware component. For example, to access hardware component A 108, each of the hardware engine A 102, hardware engine M 104, and hardware engine Y 106 would make a request to the arbitration logic A 108a. Such requests are shown by the dotted arrow from each of the hardware engine A 102, hardware engine M 104 and hardware engine Y 106 to the arbitration logic A 108a. The arbitration logic A 108a may then arbitrate among the three requests based on various arbitration criteria and select one of the hardware engines to grant access, for example access is granted to hardware engine A 102, and putting the other two hardware engines, for example hardware engine M 104 and hardware engine Y 106, on hold. After the hardware engine A 102 has completed its access to hardware component A 108, the arbitration logic A 108a may then grant access to one of the other hardware components that are put on hold based on the arbitration criteria. In this system, in order to make an arbitration decision, each arbitration logic is required to have sufficient information about all the hardware engines that may access the hardware component associated with the arbitration logic. As the number of hardware engines increases, the complexity of this arbitration scheme also increases.
FIG. 1B illustrates modifications to the conventional system of FIG. 1A when a hardware engine is added. In FIG. 1B, the plurality of hardware components remain the same as in FIG. 1A. However, a new hardware engine, namely hardware engine Z 112, is added to this conventional system for arbitration of parallel multi-event processing. Due to this addition, the arbitration logic associated with each of the hardware component needs to be modified in order for them to work with the newly added hardware engine Z 112. As shown in FIG. 1B, the modified arbitration logic A′ 108b would replace the arbitration logic A 108a in FIG. 1A. Similarly, the modified arbitration logic Y′ 110b would replace the arbitration logic Y 110a in FIG. 1A. From this example, it is evident that it is burdensome to update each of the arbitration logic associated with each hardware component when a new engine is added. In a system where the number of hardware components are large, the burden of modifying their associated arbitration logic is further amplified.
FIG. 1C illustrates modifications to the conventional system of FIG. 1A when a hardware component is added. In FIG. 1C, the plurality of hardware engines remain the same as in FIG. 1A. However, a new hardware component, namely hardware component Z 114, is added to this conventional system for arbitration of parallel multi-event processing. To make this addition, the arbitration logic Z 114a associated with the hardware component Z 114 needs to be configured to work with all existing hardware engines, such as hardware engine A 102, hardware engine M 104, and hardware engine Y 106. This is illustrated with each of the arrow from hardware engine A 102, hardware engine M 104, and hardware engine Y 106 to the arbitration logic Z 114a, respectively. In a system where the number of hardware engines are large, the complexity of such arbitration scheme also increases accordingly.
Therefore, there is a need for methods and systems that address the issues of the conventional system in a parallel multi-event processing environment as described above. Specifically, there is a need for methods and systems for arbitration of parallel multi-event processing.